A SystemC Cache Simulator for a Multiprocessor Shared Memory System

Mutanga, Alfred

doi:10.18052/www.scipress.com/ILSHS.13.75

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A SystemC Cache Simulator for a Multiprocessor Shared Memory System

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Abstract:

In this research we built a SystemC Level-1 data cache system in a distributed shared memory architectural environment, with each processor having its own local cache. Using a set of Fast-Fourier Transform and Random trace files we evaluated the cache performance, based on the number of cache hits/misses, of the caches using snooping and directory-based cache coherence protocols. A series of experiments were carried out, with the results of the experiments showing that the directory-based MOESI cache coherency protocol has a performance edge over the snooping Valid-Invalid cache coherency protocol.

Info:

Periodical:

International Letters of Social and Humanistic Sciences (Volume 13)

Pages:

75-87

DOI:

https://doi.org/10.18052/www.scipress.com/ILSHS.13.75

Citation:

A. Mutanga, "A SystemC Cache Simulator for a Multiprocessor Shared Memory System", International Letters of Social and Humanistic Sciences, Vol. 13, pp. 75-87, 2014

Online since:

October 2013

Authors:

Alfred Mutanga

Keywords:

Cache Coherency, Cache Simulator, Multiprocessor Architectures

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Distribution:

Open Access

This work is licensed under a
Creative Commons Attribution 4.0 International License

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