Subscribe

Subscribe to our Newsletter and get informed about new publication regulary and special discounts for subscribers!

ILSHS > Volume 13 > A SystemC Cache Simulator for a Multiprocessor...
< Back to Volume

A SystemC Cache Simulator for a Multiprocessor Shared Memory System

Removed due to plagiarism

Full Text PDF

Abstract:

In this research we built a SystemC Level-1 data cache system in a distributed shared memory architectural environment, with each processor having its own local cache. Using a set of Fast-Fourier Transform and Random trace files we evaluated the cache performance, based on the number of cache hits/misses, of the caches using snooping and directory-based cache coherence protocols. A series of experiments were carried out, with the results of the experiments showing that the directory-based MOESI cache coherency protocol has a performance edge over the snooping Valid-Invalid cache coherency protocol.

Info:

Periodical:
International Letters of Social and Humanistic Sciences (Volume 13)
Pages:
75-87
Citation:
A. Mutanga, "A SystemC Cache Simulator for a Multiprocessor Shared Memory System", International Letters of Social and Humanistic Sciences, Vol. 13, pp. 75-87, 2014
Online since:
October 2013
Authors:
Export:
Distribution:
References:

[1] Bartolini S., Giorgi R., Journal of Embedded Computing 2 (2003) 137-139.

[2] Bhasker J. (2009). The SystemC TM Primer. Allentown, Star Galaxy Publishers.

[3] Black C., D., Donovan J (2004). SystemC from the Ground Up, Boston, Kluwer Publishers.

[4] Byler J. (2009). Software Programmers face Multicore Challenges, in Embedded Intel.

[5] Chevance J. R. (2006). Servers Architectures: Multiple Processors, Clusters, Parallel Systems, Web Servers, Storage Solutions, London, Elsevier.

[6] Duller A. P. G., Towner D. (2003). Parallel Processing - the picoChip way! . In: Broenik, J., F And Hilderink, G. (ed.) Communicating Process Architectures. London: PicoChip.

[7] Hennessy L. J., Patterson A. D (2007). Computer Architecture. A Quantitative Approach, San Francisco, Morgan Kaufmann.

[8] Hill D., Smith A. J., IEEE Transactions on Computers 40 (1991) 371-390.

[9] Hill D., Smith A. J., IEEE Transactions on Computers 38 (1991) 1612-1630.

[10] Hobson R., Cheung K. L., Ressi B.,Signal Processing with Teams of Embedded Workhorse Processors. EURASIP Journal on Embedded Systems (2006) 16.

DOI: https://doi.org/10.1155/es/2006/69484

[11] Jesshope C. R. (2008). A model for the design and programming of multi-cores. In: GRANDINETTI, L. (ed.) Advances in Parallel Computing, 16, High performance Computing and Grids in Action London: IOS Press.

[12] Jesshope C. R (2009). Multiprocessor Memory Systems, Amsterdam Universiteit van Amsterdam.

[13] Jesshope C. R .(2011). A SystemC Tutorial. Amsterdam, Universiteit van Amsterdam.

[14] Joubert G. R. (2008). Parallel computing current and future issues of high end computing,, Forschungszentrum, John von Neumann Institute for Computing Jülich.

[15] Leiserson C. E, Mirman I. B. (2008). How to Survive the Survive Multicore Software Revolution [or at Least Survive the Hype]. . In: CLICKARTS, I. (ed.). New York: Click Arts Inc.

[16] Ma N., Modelling and evaluation of multi-core multithreaded processor architectures in SystemC,, Proquest, (2011) 1109.

[17] Mckee A. S. (2004). Reflections on the Memory Wall. In: ACM, ed. Proceedings of the 1st conference on Computing frontiers (CF '04). 2004 New York. New York: ACM, 1-6.

[18] Nussbaum S., Smith J. E. (2002). Statistical Simulation of Symmetric Multiprocessor Systems. In: IEEE, ed. In Proceedings of the 35th Annual Simulation Symposium (SS '02) , 2002. Washington, DC, USA, 89. IEEE Computer Society, 89-97.

DOI: https://doi.org/10.1109/simsym.2002.1000093

[19] OSCI. (2005). An Introduction to System Level Modelling in SystemC 2.0. Available: www.es.ele.tue.nl/~heco/courses/EmbSystems/WhitePaper20.pdf.

[20] Panesar G. T. D., Duller A., Gray A., Robins W. (2005). Deterministic Parallel Processing. In: BROENIK, J., F AND HILDERINK, G. (ed.) Microgrid workshop- 2005. London: IOS Press.

[21] Panesar G. T. D., Duller A., Gray A., Robins W., International Journal of Parallel Programming 34(4) (2006) 323-341.

[22] PICOCHIP. (2007). Technical White Paper: Practical, Programmable Multi-Core DSP. Available: http://www.picochip.com/downloads/4eac6c97aa70840ad7f4d12aec82ebf1/Multicore_June_2007.pdf [Accessed 13 March 2013].

[23] Schintke F., Simon J., Reinfield A. (2012). A Cache Simulator for Shared Memory Systems (unpublished paper).

[24] Stalling W. (2012) Computer Organization and Architecture London, Prentice Hall.

[25] Sutter H. 2005. The free lunch is over: A fundamental turn toward concurrency in software. [Online]. New York. Available: http://www.gotw.ca/publications/concurrency-ddj.htm [Accessed 13 March 2013 2013].

[26] Szydlowski C. (2005). Multithreaded Technology & Multicore Processors [Online]. New York: Dr. Dobb's. Available: http://www.drdobbs.com/multithreaded-technology-multicore.../18440607.

[27] Towner D. P. G., Duller A., Gray A., Robins W. (2004). Debugging and Verification of Parallel Systems - the picoChip way! In: BROENIK, J., F AND HILDERINK, G. (ed.) Communicating Process Architectures London: IOS Press. ( Received 04 October 2013; accepted 21 October 2013 ).

Show More Hide
Cited By:
This article has no citations.