In this work, porous silicon layers were fabricated on p-type crystalline silicon wafers using electrochemical etching ECE process. Al films were deposited onto porous layer /Si wafers by thermal evaporation to form rectifying junction. An investigation of the dependence on applied etching time to formed PS layer was studied. Effect etching time on the electrical properties of porous silicon is checked using Current–voltage I–V characteristics. The ideality factor and dynamic resistances are found to be large than the one and 20 (kΩ) respectively by the analysis of the dark I–V characteristics of Al/PS/p-Si heterojunction.
International Letters of Chemistry, Physics and Astronomy (Volume 72)
H. A. Hadi "Impact of Etching Time on Ideality Factor and Dynamic Resistance of Porous Silicon Prepared by Electrochemical Etching (ECE)", International Letters of Chemistry, Physics and Astronomy, Vol. 72, pp. 28-36, 2017